Hardware fundamentals part 3 - The Arithmethic & Logic Unit

The Arithmetic & Logic Unit (ALU) is a component that combines multiple smaller components through hardwired circuits, each carrying out a specific operation. They are all related to logic and calculation (hence the name). The idea is that the ALU is designed to carry out only simple operations, but because it can do so many in a very short time frame, more complex logic can be carried out quickly. This should be orchestrated from the outside (by the CPU) by chaining these simple operations and calling the ALU multiple times.

It can perform bitwise operations (AND, OR, XOR, etc.) and also arithmetic operations (add, subtract, increment, decrement, etc.). In addition, there are dedicated components for bitshifting (left and right), which are basically just two registers with wires in between that do not connect all outputs from R1 straight to the inputs of R2, but instead shift the connections left or right by one so bits end up one place to the left or right within the byte (effectively multiplying or dividing the resulting number by two respectively). It can also compare operands and get the two’s complement of a binary number (effectively negating and signing the value).

Two status registers are relevant for the ALU: the temporary (TMP) register which is used for the first operand of an operation if two operands are required (because only one memory register can be active on the bus at one time, we need a temporary one within the ALU) and the accumulator (ACC), which stores the output of the current ALU operation.

In addition to the ALU, which deals exclusively with integers, many modern architectures have a dedicated unit similar to the ALU but for floating point numbers, called the Floating Point Unit (FPU).

Opcodes

Opcodes (operation codes) are bitpatterns that the CPU sets to carry out operations through its internal wiring. Some of these opcodes are instructions to move data and some of these opcodes are instructions for the ALU. It is set on a bus that goes through a decoder and depending on the output of that decoder, the signal is routed on the circuit that matches the operation to be carried out. The width of the bus (n wires) determines the number of discrete operations (2^n) that can be carried out.

How a CPU carries out an instruction

Actually carrying out an operation is a sequence of steps.

If an operation requires only a single operand, the CPU does the following:

  • Enable the register containing the value of the first operand
  • Set the opcode of the ALU
  • Set the ACC register

If two operands are required, an additional step is required:

  • Enable the register containing the value of the first operand
  • Set the TMP register with this value
  • Enable the register containing the value of the second operand
  • Set the opcode of the ALU
  • Set the ACC register

The ACC can then be enabled on the bus again and set as an input operand for a subsequent operation, or do whatever is required in the sequence to carry out the more complex operation.

Flags

Another thing that is part of the ALU is the FLAGS register, which contains flag bits determining if a certain property holds true at that time. For instance, the shift and add operations use the CARRY flag as input and output do determine if something else other than the input operands play a role in the result set to the ACC, such as carrying over when adding numbers together (like you would when doing addition on paper by the rules: 7 + 5 means write down a 2 and carry over a 1 to add to the tens digit, making 12).

There are also flags for use in the CMP (compare) operation, which either sets the EQUALS flag to 1 if the two operands are equal, or ALARGER if the first operand was larger than the second. If both are 0, operand b was larger. These equality flags are used when doing conditional jumps (you may know about the assembly instructions JE (jump if equal), JNE (jump if not equal), JZ (jump if zero), JNZ (jump if not zero), etc.)

Now, let’s move on to how this comes together for orchestration of more complex operations!